1. Field of the Invention
The present invention relates generally to integrated circuits, particularly to a semiconductor or glass substrate-based carrier for mounting and packaging multiple integrated circuit chips and/or other devices.
2. Description of Related Art
Formation and metallization of deep vias in silicon (Si) substrates used for packaging applications is difficult to achieve with the current state-of-the-art processes. One obstacle has been the via size requirement for packaging applications, which is typically much larger than a via used in VLSI device applications. After a via has been metallized, the larger sized via can cause high thermal-mechanical stresses within the surrounding structure. Metallization of vias in silicon is typically achieved using either metal deposition, such as plasma vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), chemical plating, or a combination of these techniques. The resultant via is metallized with essentially pure metals or metal alloys. The high coefficient of thermal expansion (CTE) of metal, along with a relatively high elastic modulus, results in high thermal-mechanical stress within the via and within the surrounding silicon. The high stress levels can form cracks within the surrounding silicon and/or cause interfacial failure at the via metal/silicon interface.
One solution to this problem has been to utilize lower CTE composite material(s) to fill the via. Filling via holes in silicon with a composite material involves making a composite paste or suspension and then filling the via hole with the paste/suspension. A sintering step is required to “densify” the conductive component of the composite via. Since the composite paste or suspension is comprised of particles, complete, solid filling of the via holes is not possible. Typically, the porosity of the composite paste-filled via is about forty to fifty percent. This means the via can trap liquids and contaminants in its pore-network. The trapped materials will ultimately outgas and volatilize in subsequent processing steps and create severe problems. Thus, a method to seal the via porosity is necessary to prevent the ingress of liquids and contaminants. Additionally, the sealed via must be able to withstand all downstream processes required for fabrication of the silicon carrier as well as chip attachment. FIG. 1 depicts a exploded portion of a paste-filled via 300 after blanket metallization without a via seal. Structures 310 develop during post metallization high temperature excursion where liquid penetrant is volatilized, bringing with it components of the paste, which then solidify on the surface during the high temperature excursion.